Input 333M-800MHz, output 333M-800MHz, all digital DLL with per 1/64UI programmable delay, UMC 55nm SP/RVT Low-K Logic process. View DLL (All Digital) IP, Input: 333MHz - 800MHz, Output: 333MHz - ...
3.3V with 150mA driving capability, Istb=96uA Linear Regulator, UMC 0.18um GII Logic process. View Linear Regulator IP, Input: 2.0V - 3.9V, Output: 1.8V / 150mA, Iq=66uA, Idis=1uA, UMC 0.18um G2 ...
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