Austin, Texas — LSI Logic Corp. has added a measure of packaging flexibility to its ASIC design flow, allowing customers to design a single die that can quickly move from a wirebond to a ...
Kulicke & Soffa Industries Inc. (K&S) today announced that Amkor Technology Inc. of Chandler, Ariz., will license its wafer level packaging technology from Flip Chip Technologies LLC (FCT) for its ...
New bump structures are being developed to enable higher interconnect densities in flip-chip packaging, but they are complex, expensive, and increasingly difficult to manufacture. For products with ...
Copper (Cu) redistribution layer (RDL) technology is used to interconnect chips in various high current Wafer Level Packaging (WLP) applications. Typically, Cu RDLs with thicknesses of 5-9 µm and ...
Recognizing the strategic importance of semiconductor packaging technology, the South Korean government is reportedly initiating a major packaging technology R&D project aimed at assisting companies ...
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